Senior Analog Layout Engineer

• Perform full‑custom analog layout for critical circuit blocks, including:

• Analog Front Ends (AFEs)
• ADCs and DACs
• PLLs and clocking circuits
• Voltage regulators and references
• Analog filters and bias circuits
• Translate schematics into high‑quality, silicon‑proven layouts in advanced nodes.
• Apply best‑in‑class techniques for:

• Matching and symmetry
• Parasitic control
• Noise isolation and substrate coupling mitigation
• EM/IR and reliability robustness

• Run and debug DRC, LVS, ERC, and reliability checks.
• Work with designers to close LVS and performance issues.
• Support PEX extraction and simulation correlation.
• Ensure layouts meet foundry design rules and sign‑off requirements.

• Partner closely with analog circuit designers, CAD, and methodology teams.
• Participate in layout and design reviews.
• Support silicon bring‑up, debug, and yield improvement as needed.
• Contribute to layout guidelines, documentation, and best practices.

• BSEE or equivalent in Electrical / Electronics Engineering (preferred).

• 6–10 years of hands‑on experience in custom analog / mixed‑signal layout.
• Proven experience working in 28nm, 22nm, and/or 16nm CMOS process technologies.
• Demonstrated experience laying out complex analog IP blocks (AFE, ADC, DAC, PLL, regulators).

• Strong proficiency with:

• Cadence Virtuoso Layout Suite
• Calibre (DRC, LVS, PEX)
• Solid understanding of:

• Foundry design rules
• Device matching and layout‑dependent effects
• Parasitics, coupling, and noise mitigation
• Reliability (EM, IR, ESD awareness)
• Familiarity with advanced-node layout challenges is required.

• Experience in automotive or high‑reliability semiconductor products.
• Familiarity with low‑noise, high‑speed analog layouts.
• Ability to mentor junior layout engineers.
• Exposure to ISO / automotive quality flows is a plus.

NXP Semiconductors