
Graduate Trainee - Silicon Design Engineer (FEINT)
- Pulau Pinang
- Sementara
- Sepenuh masa
- learn front-end ASIC design skills, from writing RTL verilog, conducting RTL checks to synthesizing the RTL into netlist.
- Interact with world class global engineering
- Taking on one of more tasks involving RTL integration, design constraining, conducting formal verification and functional verification, running RTL & netlist/gate-level simulation, linting and CDC/RDC checks, synthesis
- Bachelor Degree in Engineering: Electrical & Electronics / Computer Engineering / Computer Science.